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general description the MAX1427 is a 5v, high-speed, high-performance analog-to-digital converter (adc) featuring a fully differ- ential wideband track-and-hold (t/h) and a 15-bit con- verter core. the MAX1427 is optimized for multichannel, multimode receivers, which require the adc to meet very stringent dynamic performance requirements. with a noise floor of -79.3dbfs, the MAX1427 allows for the design of receivers with superior sensitivity. the MAX1427 achieves two-tone, spurious-free dynamic range (sfdr) of -91dbc for input tones of 10mhz and 15mhz. its excellent signal-to-noise ratio (snr) of 76.1db and single-tone sfdr performance (sfdr1/sfdr2) of 93.5dbc/94.5dbc at f in = 15mhz and a sampling rate of 80msps make this part ideal for high-performance digital receivers. the MAX1427 operates from an analog 5v and a digital 3v supply, features a 2.56v p-p full-scale input range, and allows for a sampling speed of up to 80msps. the input t/h operates with a -1db full-power bandwidth of 200mhz. the MAX1427 features parallel, cmos-compatible out- puts in two?-complement format. to enable the interface with a wide range of logic devices, this adc provides a separate output driver power-supply range of 2.3v to 3.5v. the MAX1427 is manufactured in an 8mm x 8mm, 56-pin qfn package with exposed paddle (ep) for low thermal resistance, and is specified for the extended industrial (-40? to +85?) temperature range. note that if parts max1418, max1428, and max1430 (see pin-compatible higher/lower speed versions selection table) are recommended for applications that require high dynamic performance for input frequen- cies greater than f clk /3. the MAX1427 is optimized for input frequencies of less than f clk /3. applications cellular base-station transceiver systems (bts) wireless local loop (wll) single- and multicarrier receivers multistandard receivers e911 location receivers power amplifier linearity correction antenna array processing features 80msps minimum sampling rate -79.3dbfs noise floor excellent dynamic performance 76.1db snr at f in = 15mhz and a in = -1dbfs 93.5dbc/94.5dbc single-tone sfdr1/sfdr2 at f in = 15mhz and a in = -1dbfs -91dbc multitone sfdr at f in1 = 10mhz and f in2 = 15mhz less than 0.25ps sampling jitter fully differential analog input voltage range of 2.56v p-p cmos-compatible two?-complement data output separate data valid clock and overrange outputs flexible-input clock buffer ev kit available for MAX1427 (order MAX1427evkit) MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications ________________________________________________________________ maxim integrated products 1 ordering information 19-3010; rev 0; 10/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin configuration appears at end of data sheet. part temp range pin-package MAX1427etn -40 c to +85 c 56 qfn-ep* pin-compatible higher/lower speed versions selection part speed grade (msps) target application max1418 65 if max1419 65 baseband MAX1427 80 baseband max1428* 80 if max1429* 100 baseband max1430* 100 if * future product?ontact factory for availability. * ep = exposed paddle.
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av cc = 5v, dv cc = drv cc = 2.5v, gnd = 0, inp and inn driven differentially with -1dbfs, clkp and clkn driven differentially with a 2v p-p sinusoidal input signal, c l = 5pf at digital outputs, f clk = 80mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and char- acterization.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc , dv cc , drv cc to gnd.................................. -0.3v to +6v inp, inn, clkp, clkn, cm to gnd........-0.3v to (av cc + 0.3v) d0 d14, dav, dor to gnd..................-0.3v to (drv cc + 0.3v) continuous power dissipation (t a = +70 c) 56-pin qfn (derate 47.6mw/ c above +70 c) ......3809.5mw operating temperature range ...........................-40 c to +85 c thermal resistance j a ...................................................21 c/w junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy resolution 15 bits integral nonlinearity inl f in = 15mhz 1.5 lsb differential nonlinearity dnl f in = 15mhz, no missing codes guaranteed 0.4 lsb offset error -12 +12 mv gain error -4 +4 %fs analog input (inp, inn) d i ffer enti al inp ut v ol tag e rang ev diff fully differential inputs drive, v diff = v inp - v inn 2.56 v p-p common-mode input voltage v cm self-biased 3.38 v differential input resistance r in 1 15% k ? differential input capacitance c in 1pf full-power analog bandwidth fpbw -1db -1db rolloff for a full-scale input 200 mhz conversion rate maximum clock frequency f clk 80 mhz minimum clock frequency f clk 20 mhz aperture jitter t aj 0.21 ps rms clock input (clkp, clkn) full-scale differential input voltage v diffclk 0.5 to 3.0 v common-mode input voltage v cm self-biased 2.4 v differential input resistance r inclk 2 15% k ? differential input capacitance c inclk 1pf dynamic characteristics thermal + quantization noise floor nf analog input <-35dbfs -79.3 dbfs f in = 5mhz at -1dbfs 76.5 f in = 15mhz at -1dbfs 73.5 76.1 signal-to-noise ratio (note 1) snr f in = 35mhz at -1dbfs 75.6 db
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications _______________________________________________________________________________________ 3 electrical characteristics (continued) (av cc = 5v, dv cc = drv cc = 2.5v, gnd = 0, inp and inn driven differentially with -1dbfs, clkp and clkn driven differentially with a 2v p-p sinusoidal input signal, c l = 5pf at digital outputs, f clk = 80mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and char- acterization.) parameter symbol conditions min typ max units f in = 5mhz at -1dbfs 76.3 f in = 15mhz at -1dbfs 73 75.9 signal-to-noise and distortion (note 1) f in = 35mhz at -1dbfs 75.3 db f in = 5mhz at -1dbfs 96.5 f in = 15mhz at -1dbfs 84 93.5 spurious-free dynamic range (hd2 and hd3) (note 1) sfdr1 f in = 35mhz at -1dbfs 85 dbc f in = 5mhz at -1dbfs 94.5 f in = 15mhz at -1dbfs 85.5 94.5 spurious-free dynamic range (hd4 and higher) (note 1) sfdr2 f in = 35mhz at -1dbfs 91 dbc two-tone intermodulation distortion ttimd f in1 = 10mhz at -7dbfs; f in2 = 15mhz at -7dbfs -91 dbc two-tone spurious-free dynamic range sfdr tt f in1 = 10mhz at -10dbfs < f in1 < -100dbfs; f in2 = 15mhz at -10dbfs < f in2 < -100dbfs -105 dbfs digital outputs (d0 d14, dav, dor) digital output voltage low v ol 0.5 v digital output voltage high v oh dv cc - 0.5 v timing characteristics (dv cc = drv cc = 2.5v) figure 4 clkp/clkn duty cycle duty cycle 50 5 % effective aperture delay t ad 230 ps output data delay t dat (note 3) 3 4.5 7.5 ns data valid delay t dav (note 3) 5.3 6.5 8.7 ns pipeline latency t latency 3 clock cycles clkp rising edge to data not valid t dnv (note 3) 2.6 3.8 5.7 ns clkp rising edge to data valid (guaranteed) t dgv (note 3) 3.4 5.2 8.6 ns data setup time (before dav rising edge) t setup (note 3) t clkp - 0.5 t clkp + 1.3 t clkp + 2.4 ns data hold time (after dav rising edge) t hold (note 3) t clkn - 3.6 t clkn - 2.8 t clkn - 2.0 ns
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications 4 _______________________________________________________________________________________ note 1: dynamic performance is based on a 32,768-point data record with a sampling frequency of f sample = 80.019456mhz, an input frequency of f in = f sample x (6143/32768) = 15.001206mhz, and a frequency bin size of 2442hz. close-in (f in 29.3khz) and low-frequency (dc to 58.6khz) bins are excluded from the spectrum analysis. note 2: apply the same voltage levels to dv cc and drv cc . note 3: guaranteed by design and characterization. electrical characteristics (continued) (av cc = 5v, dv cc = drv cc = 2.5v, gnd = 0, inp and inn driven differentially with -1dbfs, clkp and clkn driven differentially with a 2v p-p sinusoidal input signal, c l = 5pf at digital outputs, f clk = 80mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and char- acterization.) parameter symbol conditions min typ max units timing characteristics (dv cc = drv cc = 3.3v) figure 4 clkp/clkn duty cycle duty cycle 50 5 % effective aperture delay t ad 230 ps output data delay t dat (note 3) 2.8 4.1 6.5 ns data valid delay t dav (note 3) 5.3 6.3 8.6 ns pipeline latency t latency 3 clock cycles clkp rising edge to data not valid t dnv (note 3) 2.5 3.4 5.2 ns clkp rising edge to data valid (guaranteed) t dgv (note 3) 3.2 4.4 7.4 ns data setup time (before dav rising edge) t setup (note 3) t clkp + 0.2 t clkp + 1.7 t clkp + 2.8 ns data hold time (after dav rising edge) t hold (note 3) t clkn - 3.5 t clkn - 2.7 t clkn - 2.0 ns power requirements analog supply voltage range av cc 5 3% v digital supply voltage range dv cc (note 2) 2.3 to 3.5 v output supply voltage range drv cc (note 2) 2.3 to 3.5 v analog supply current i avcc 377 440 ma d i g i tal + outp ut s up p l y c ur r ent i dvcc + f clk = 80mhz, c load = 5pf 35.5 42 ma analog power dissipation pdiss 1974 mw
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications _______________________________________________________________________________________ 5 fft plot (32,768-point data record, coherent sampling) MAX1427 toc01 analog input frequency (mhz) amplitude (dbfs) 25 20 15 10 5 -100 -80 -60 -40 -20 0 -120 040 35 30 f clk = 80.0195mhz f in = 9.9999mhz a in = -1.04dbfs snr = 76.3db sfdr1 = 96.2dbc sfdr2 = 98.91dbc hd2 = -102.5dbc hd3 = -96.2dbc fft plot (32,768-point data record, coherent sampling) MAX1427 toc02 analog input frequency (mhz) amplitude (dbfs) 25 20 15 10 5 -100 -80 -60 -40 -20 0 -120 040 35 30 f clk = 80.0195mhz f in = 15.0012mhz a in = -1.00dbfs snr = 76db sfdr1 = 94.7dbc sfdr2 = 94.7dbc hd2 = -94.7dbc hd3 = -104.8dbc fft plot (32,768-point data record, coherent sampling) MAX1427 toc03 analog input frequency (mhz) amplitude (dbfs) 25 20 15 10 5 -100 -80 -60 -40 -20 0 -120 040 35 30 f clk = 80.0195mhz f in = 35.0012mhz a in = -1.02dbfs snr = 75.5db sfdr1 = 84.4dbc sfdr2 = 87dbc hd2 = -84.4dbc hd3 = -91.6dbc snr vs. analog input frequency (f clk = 80.0195mhz, a in = -1dbfs) MAX1427 toc04 f in (mhz) snr (db) 55 45 15 25 35 71 72 73 74 75 76 77 78 70 575 70 65 sfdr1/sfdr2 vs. analog input frequency (f clk = 80.0195mhz, a in = -1dbfs) MAX1427 toc05 f in (mhz) sfdr1/sfdr2 (dbc) 55 45 35 25 15 75 80 85 90 95 100 70 575 70 65 sfdr2 sfdr1 hd2/hd3 vs. analog input frequency (f clk = 80.0195mhz, a in = -1dbfs) MAX1427 toc06 f in (mhz) hd2/hd3 (dbc) 55 45 35 25 15 -100 -95 -90 -85 -80 -75 -110 -105 575 70 65 hd2 hd3 full-scale-to-noise ratio vs. analog input amplitude (f clk = 80.0195mhz, f in = 15.0012mhz) MAX1427 toc07 analog input amplitude (dbfs) full-scale-to-noise ratio (dbfs) -10 -20 -40 -30 -50 -60 71 72 73 74 75 76 77 78 79 80 70 -70 0 sfdr1/sfdr2 vs. analog input amplitude (f clk = 80.0195mhz, f in = 15.0012mhz) MAX1427 toc08 analog input amplitude (dbfs) sfdr1/sfdr2 (dbfs) -10 -20 -40 -30 -50 -60 80 90 100 110 120 130 70 -70 0 sfdr1 sfdr2 hd2/hd3 vs. analog input amplitude (f clk = 80.195mhz, f in = 15.00102mhz) MAX1427 toc09 analog input amplitude ( dbfs ) hd2/hd3 (dbfs) -10 -20 -40 -30 -50 -60 -120 -110 -100 -90 -80 -70 -150 -140 -130 -70 0 hd2 hd3 typical operating characteristics (av cc = 5v, dv cc = drv cc = 2.5v, inp and inn driven differentially with a -1dbfs amplitude, clkp and clkn driven differentially with a 2v p-p sinusoidal input signal, c l = 5pf at digital outputs, f clk = 80mhz, t a = +25 c. all ac data based on a 32k-point fft record and under coherent sampling conditions.)
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications 6 _______________________________________________________________________________________ snr vs. sampling frequency (f in = 15.2mhz, a in = -1dbfs) MAX1427 toc10 f clk (mhz) snr (db) 30 40 50 70 60 80 71 72 73 74 75 76 77 78 20 sfdr1/sfdr2 vs. sampling frequency (f in = 15.2mhz, a in = -1dbfs) MAX1427 toc11 f clk (mhz) sfdr1/sfdr2 (dbc) 80 70 60 50 40 30 75 80 85 90 95 100 70 20 sfdr1 sfdr2 hd2/hd3 vs. sampling frequency (f in = 15.2mhz, a in = -1dbfs) MAX1427 toc12 f clk (mhz) hd2/hd3 (dbc) 70 50 30 40 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -120 20 80 60 hd3 hd2 snr vs. temperature (f clk = 80.0195mhz, f in = 15.0012mhz, a in = -1dbfs) MAX1427 toc13 temperature ( c) snr (db) 60 35 10 -15 74 75 76 77 78 73 -40 85 sinad vs. temperature (f clk = 80.0195mhz, f in = 15.0012mhz, a in = -1dbfs) MAX1427 toc14 temperature ( c) sinad (db) 60 35 10 -15 74 75 76 77 78 71 72 73 -40 85 typical operating characteristics (continued) (av cc = 5v, dv cc = drv cc = 2.5v, inp and inn driven differentially with a -1dbfs amplitude, clkp and clkn driven differentially with a 2v p-p sinusoidal input signal, c l = 5pf at digital outputs, f clk = 80mhz, t a = +25 c. all ac data based on a 32k-point fft record and under coherent sampling conditions.)
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications _______________________________________________________________________________________ 7 two-tone imd plot (32,768-point data record, coherent sampling) MAX1427 toc19 analog input frequency (mhz) amplitude (dbfs) 25 20 15 10 5 -100 -80 -60 -40 -20 0 -120 035 30 40 f clk = 80.0195mhz f in1 = 10.0010mhz f in2 = 15.0010mhz a in1 = a in2 = -7dbfs 2f in1 - f in2 2f in2 - f in1 f in1 f in2 sfdr1/sfdr2 vs. temperature (f clk = 80.0195mhz, f in = 15.0012mhz, a in = -1dbfs) MAX1427 toc15 temperature ( c) sfdr1/sfdr2 (dbc) 60 35 10 -15 80 85 90 95 100 75 -40 85 sfdr1 sfdr2 hd2/hd3 vs. temperature (f clk = 80.0195mhz, f in = 15.0012mhz, a in = -1dbfs) MAX1427 toc16 temperature ( c) hd2/hd3 (dbc) 60 35 10 -15 -100 -95 -90 -85 -80 -110 -105 -40 85 hd2 hd3 power dissipation vs. temperature (f clk = 80.0195mhz, f in = 15.0012mhz, a in = -1dbfs) MAX1427 toc17 temperature ( c) power dissipation (mw) 60 35 10 -15 1969 1973 1977 1981 1985 1965 -40 85 power dissipation vs. supply voltage (f clk = 80.0195mhz, f in = 15.0012mhz, a in = -1dbfs) MAX1427 toc18 supply voltage (v) power dissipation (mw) 5.20 5.15 4.90 4.95 5.00 5.05 5.10 1850 1900 1950 2000 2050 2100 2150 2200 1800 4.85 5.25 typical operating characteristics (continued) (av cc = 5v, dv cc = drv cc = 2.5v, inp and inn driven differentially with a -1dbfs amplitude, clkp and clkn driven differentially with a 2v p-p sinusoidal input signal, c l = 5pf at digital outputs, f clk = 80mhz, t a = +25 c. all ac data based on a 32k-point fft record and under coherent sampling conditions.)
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications 8 _______________________________________________________________________________________ pin description pin name function 1, 2, 3, 6, 9, 12, 14 17, 20, 23, 26, 27, 30, 52 56, ep gnd converter ground. analog, digital, and output driver grounds are internally connected to the same potential. connect the converter s ep to gnd. 4 clkp differential clock, positive input terminal 5 clkn differential clock, negative input terminal 7, 8, 18, 19, 21, 22, 24, 25, 28 av cc analog supply voltage. provide local bypassing to ground with 0.1f to 0.22f capacitors. 10 inp differential analog input, positive terminal 11 inn differential analog input, negative/complementary terminal 13 cm common-mode reference terminal 29 dv cc digital supply voltage. provide local bypassing to ground with 0.1f to 0.22f capacitors. 31, 41, 42, 51 drv cc digital output driver supply voltage. provide local bypassing to ground with 0.1f to 0.22f capacitors. 32 dor data overrange bit. this control line flags an overrange condition in the adc. if dor transitions high, an overrange condition is detected. if dor remains low, the adc operates within the allowable full-scale range. 33 d0 digital cmos output bit 0 (lsb) 34 d1 digital cmos output bit 1 35 d2 digital cmos output bit 2 36 d3 digital cmos output bit 3 37 d4 digital cmos output bit 4 38 d5 digital cmos output bit 5 39 d6 digital cmos output bit 6 40 d7 digital cmos output bit 7 43 d8 digital cmos output bit 8 44 d9 digital cmos output bit 9 45 d10 digital cmos output bit 10 46 d11 digital cmos output bit 11 47 d12 digital cmos output bit 12 48 d13 digital cmos output bit 13 49 d14 digital cmos output bit 14 (msb) 50 dav data valid output. this output can be used as a clock control line to drive an external buffer or data-acquisition system. the typical delay time between the falling edge of the converter clock and the rising edge of dav is 6.5ns.
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications _______________________________________________________________________________________ 9 detailed description figure 1 provides an overview of the MAX1427 archi- tecture. the MAX1427 employs an input t/h amplifier, which has been optimized for low thermal noise and low distortion. the high-impedance differential inputs to the t/h amplifier (inp and inn) are self-biased at 3.38v, and support a full-scale differential input voltage of 2.56v p-p . the output of the t/h amplifier is fed to a multistage pipelined adc core, which has also been optimized to achieve a very low thermal noise floor and low distortion. a clock buffer receives a differential input clock wave- form and generates a low-jitter clock signal for the input t/h. the signal at the analog inputs is sampled at the rising edge of the differential clock waveform. the dif- ferential clock inputs (clkp and clkn) are high- impedance inputs, are self-biased at 2.4v, and support differential clock waveforms from 0.5v p-p to 3.0v p-p . the outputs from the multistage pipelined adc core are delivered to error correction and formatting logic, which in turn, deliver the 15-bit output code in two s- complement format to digital output drivers. the output drivers provide cmos-compatible outputs with levels programmable over a 2.3v to 3.5v range. analog inputs and common mode (inp, inn, cm) the signal inputs to the MAX1427 (inp and inn) are balanced differential inputs. this differential configura- tion provides immunity to common-mode noise coupling and rejection of even-order harmonic terms. the differ- ential signal inputs to the MAX1427 should be ac-cou- pled and carefully balanced in order to achieve the best dynamic performance (see the applications information section for more detail). ac-coupling of the input signal is easily accomplished because the MAX1427 inputs are self-biasing as illustrated in figure 2. although the t/h inputs are high impedance, the actual differential input impedance is nominally 1k ? because of the two 500 ? bias resistors connected from each input to the common-mode reference. the cm pin provides a monitor of the input common- mode self-bias potential. in most applications, in which the input signal is ac-coupled, this pin is not connect- ed. if dc-coupling of the input signal is required, this pin may be used to construct a dc servo loop to con- trol the input common-mode potential. see the applications information section for more details. t/h correction logic + output buffers internal timing internal reference inp inn cm clkp clkn dav 15 data bits d0 through d14 av cc drv cc dv cc gnd multistage pipeline adc core clock buffer MAX1427 figure 1. simplified MAX1427 block diagram buffer internal reference and biasing circuit t/h amplifier t/h amplifier 500 ? 500 ? cm inp inn to 1. quantizer stage to 1. quantizer stage 1k ? figure 2. simplified analog and common-mode input architecture
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications 10 ______________________________________________________________________________________ on-chip reference circuit the MAX1427 incorporates an on-chip 2.5v, low-drift bandgap reference. this reference potential establish- es the full-scale range for the converter, which is nomi- nally 2.56v p-p differential. the internal reference potential is not accessible to the user, so the full-scale range for the MAX1427 cannot be externally adjusted. figure 3 shows how the reference is used to generate the common-mode bias potential for the analog inputs. the common-mode input bias is set to one diode potential above the bandgap reference potential, and so varies over temperature. clock inputs (clkp, clkn) the differential clock buffer for the MAX1427 has been designed to accept an ac-coupled clock waveform. like the signal inputs, the clock inputs are self-biasing. in this case, the common-mode bias potential is 2.4v and each input is connected to the reference potential through a 1k ? resistor. consequently, the differential input resistance associated with the clock inputs is 2k ? . while differential clock signals as low as 0.5v p-p may be used to drive the clock inputs, best dynamic performance is achieved with clock input voltage levels of 2v p-p to 3v p-p . jitter on the clock signal translates directly to jitter (noise) on the sampled signal. therefore, the clock source should be a low-jitter (low- phase noise) source. see the applications information section for additional details on driving the clock inputs. system timing requirements figure 4 depicts the timing relationships for the signal input, clock input, data output, and dav output. the variables shown in the figure correspond to the various timing specifications in the electrical characteristics section. these include: ? t dat : delay from the rising edge of the clock until the 50% point of the output data transition ? t dav : delay from the falling edge of the clock until the 50% point of the dav rising edge ? t dnv : time from the rising edge of the clock until data is no longer valid 1ma 2ma inp/inn common-mode reference 500 ? 500 ? 1k ? 2.5v figure 3. simplified reference architecture inp inn d0?14 dor dav n + 1 n n + 2 n + 3 clkp clkn t ad t clkp t clkn n - 3 n - 2 n - 1 n t s t h t dat t dav t dnv t dgv figure 4. system and output timing diagram
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications ______________________________________________________________________________________ 11 ? t dgv : time from the rising edge of the clock until data is guaranteed to be valid ? t setup : time from data guaranteed valid until the ris- ing edge of dav ? t hold : time from the rising edge of dav until data is no longer valid ? t clkp : time from the 50% point of the rising edge to the 50% point of the falling edge of the clock signal ? t clkn : time from 50% point of the falling edge to the 50% point of the rising edge of the clock signal the MAX1427 samples the input signal on the rising edge of the input clock. output data is valid on the ris- ing edge of the dav signal, with a data latency of three clock cycles. note that the clock duty cycle must be 50% 5% for proper operation. digital outputs (d0?14, dav, dor) the logic high level of the cmos-compatible digital outputs (d0 d14, dav, and dor) may be set in the 2.3v to 3.5v range. this is accomplished by setting the voltage at the dv cc and drv cc pins to the desired logic-high level. note that the dv cc and drv cc volt- ages must be the same value. for best performance, the capacitive loading on the digital outputs of the MAX1427 should be kept as low as possible (<10pf). large capacitive loads result in large charging currents during data transitions, which may feed back into the analog section of the adc and create distortion terms. the loading capacitance is kept low by keeping the output traces short and by driving a single cmos buffer or latch input (as opposed to multiple cmos inputs). inserting small series resistors (220 ? or less) between the MAX1427 outputs and the digital load, placed as closely as possible to the output pins, is helpful in con- trolling the size of the charging currents during data transitions and can improve dynamic performance. keep the trace length from the resistor to the load as short as possible to minimize trace capacitance. the output data is in two s complement format, as illus- trated in table 1. data is valid at the rising edge of dav (figure 4), and dav may be used as a clock signal to latch the output data. the dav output provides twice the drive strength of the data outputs, and may therefore be used to drive multiple data latches. the dor output is used to identify an overrange condi- tion. if the input signal exceeds the positive or negative full-scale range for the MAX1427, then dor is asserted high. the timing for dor is identical to the timing for the data outputs, and dor therefore provides an over- range indication on a sample-by-sample basis. table 1. max1419 digital output coding inp analog voltage level inn analog voltage level d14 d0 two s complement code v ref + 0.64v v ref - 0.64v 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (positive full scale) v ref v ref 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (midscale + ) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (midscale - ) v ref - 0.64v v ref + 0.64v 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (negative full scale)
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications 12 ______________________________________________________________________________________ applications information differential, ac-coupled clock input the clock inputs to the MAX1427 are designed to be driven with an ac-coupled differential signal, and best performance is achieved under these conditions. however, it is often the case that the available clock source is single ended. figure 5 demonstrates one method for converting a single-ended clock signal into a differential signal through a transformer. in this exam- ple, the transformer turns ratio from the primary to sec- ondary side is 1:1.414. the impedance ratio from primary to secondary is the square of the turns ratio, or 1:2, so that terminating the secondary side with a 100 ? differential resistance results in a 50 ? load looking into the primary side of the transformer. the termination resistor in this example comprises the series combina- tion of two 50 ? resistors with their common node ac- coupled to ground. alternatively, a single 100 ? resistor across the two inputs with no common-mode connec- tion could be employed. in the example of figure 5, the secondary side of the transformer is coupled directly to the clock inputs. since the clock inputs are self-biasing, the center tap of the transformer must be ac-coupled to ground or left floating. if the center tap of the secondary were dc- coupled to ground, then it would be necessary to add blocking capacitors in series with the clock inputs. clock jitter is generally improved if the clock signal has a high slew rate at the time of its zero crossing. therefore, if a sinusoidal source is used to drive the clock inputs, it is desirable that the clock amplitude be as large as possible to maximize the zero-crossing slew rate. the back-to-back schottky diodes shown in figure 5 are not required as long as the input signal is held to 3v p-p differential or less. if a larger amplitude signal is provided (to maximize the zero-crossing slew rate), then the diodes serve to limit the differential sig- nal swing at the clock inputs. any differential mode noise coupled to the clock inputs translates to clock jitter and degrades the snr perfor- mance of the MAX1427. any differential mode coupling of the analog input signal into the clock inputs results in harmonic distortion. consequently, it is important that the clock lines be well isolated from the analog signal input and from the digital outputs. see the pc board layout considerations sections for more discussion on noise coupling. differential, ac-coupled analog input the analog inputs (inp and inn) are designed to be dri- ven with a differential ac-coupled signal. it is extremely important that these inputs be accurately balanced. any common-mode signal applied to these inputs degrade even-order distortion terms. therefore, any attempt at driving these inputs in a single-ended fashion results in significant even-order distortion terms. figure 6 presents one method for converting a single- ended signal to a balanced differential signal using a transformer. the primary-to-secondary turns ratio in this example is 1:1.414. the impedance ratio is the square of the turns ratio, so in this example, the impedance ratio is 1:2. in order to achieve a 50 ? input impedance at the primary side of the transformer, the secondary side is terminated with a 112 ? differential load. this load, in shunt with the differential input resistance of the MAX1427, results in a 100 ? differential load on the sec- ondary side. it is reasonable to use a larger transformer turns ratio in order to achieve a larger signal step-up, and this may be desirable in order to relax the drive requirements for the circuitry driving the MAX1427. MAX1427 50 ? 50 ? 0.1 f 0.1 f 0.01 f 0.1 f 0.01 f back-to-back diode t2-1t kk81 15 d0 d14 av cc dv cc drv cc gnd clkp clkn inp inn figure 5. transformer-coupled clock input configuration
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications ______________________________________________________________________________________ 13 however, the larger the turns ratio, the larger the effect of the differential input resistance of the MAX1427 on the primary referred input resistance. at a turns ratio of 1:4.47, the 1k ? differential input resistance of the MAX1427 by itself results in a primary referred input resistance of 50 ? . although the center tap of the transformer in figure 6 is shown floating, it may be ac-coupled to ground. however experience has shown that better balance is achieved if the center tap is left floating. as stated previously, the signal inputs to the MAX1427 must be accurately balanced to achieve the best even- order distortion performance. figure 7 provides improved balance over the circuit of figure 6 by adding a balun on the primary side of the transformer, and can yield substantial improvement in even-order distortion terms over the circuit of figure 6. one note of caution in relation to transformers is impor- tant. any dc current passed through the primary or secondary windings of a transformer may magnetically bias the transformer core. when this happens, the transformer is no longer accurately balanced and a degradation in the distortion of the MAX1427 may be observed. the core must be demagnetized in order to return to balanced operation. MAX1427 56 ? 56 ? 0.1 f 0.1 f 0.01 f t2-1t kk81 15 d0 d14 av cc dv cc drv cc gnd clkp clkn inp inn single-ended input terminal figure 6. transformer-coupled analog input configuration MAX1427 56 ? 56 ? 0.1 f 0.1 f 0.1 f t2-1t kk81 t2-1t kk81 15 d0 d14 av cc dv cc drv cc gnd clkp clkn inp inn positive terminal figure 7. transformer-coupled analog input configuration with primary-side transformer
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications 14 ______________________________________________________________________________________ dc-coupled analog input while ac-coupling of the input signal is the proper means for achieving the best dynamic performance, it is possible to dc-couple the inputs by making use of the cm potential. figure 8 shows one method for accomplishing dc-coupling. the common-mode potentials at the outputs of amplifiers oa1 and oa2 are servoed by the action of amplifier oa3 to be equal to the cm potential of the MAX1427. care must be taken to ensure that the common-mode loop is stable, and the r f /r g ratios of both half circuits must be well matched to ensure balance. pc board layout considerations the performance of any high-dynamic range, high sample-rate converter may be compromised by poor pc board layout practices. the MAX1427 is no excep- tion to the rule, and careful layout techniques must be observed in order to achieve the specified perfor- mance. layout issues are addressed in the following four categories: 1) layer assignments 2) signal routing 3) grounding 4) supply routing and bypassing the MAX1427 evaluation board (MAX1427 ev kit) pro- vides an excellent frame of reference for board layout, and the discussion that follows is consistent with the practices incorporated on the evaluation board. layer assignments the MAX1427 ev kit is a six-layer board, and the assignment of layers is discussed in this context. it is recommended that the ground plane be on a layer between the signal routing layer and the supply routing layer(s). this practice prevents coupling from the sup- ply lines into the signal lines. the MAX1427 ev kit pc board places the signal lines on the top (component) layer and the ground plane on layer 2. any region on the top layer not devoted to signal routing is filled with ground plane with vias to layer 2. layers 3 and 4 are devoted to supply routing, layer 5 is another ground plane, and layer 6 is used for the placement of addi- tional components and for additional signal routing. a four-layer implementation is also feasible using layer 1 for signal lines, layer 2 as a ground plane, layer 3 for supply routing, and layer 4 for additional signal routing. however, care must be taken to make sure that the clock and signal lines are isolated from each other and from the supply lines. signal routing in order to preserve good even-order distortion, the sig- nal lines (those traces feeding the inp and inn inputs) must be carefully balanced. to accomplish this, the sig- nal traces should be made as symmetric as possible, meaning that each of the two signal traces should be the same length and should see the same parasitic environ- ment. as mentioned previously, the signal lines must be isolated from the supply lines to prevent coupling from the supplies to the inputs. this is accomplished by mak- ing the necessary layer assignments as described in the previous section. additionally, it is crucial that the clock lines be isolated from the signal lines. on the MAX1427 ev kit, this is done by routing the clock lines on the bot- tom layer (layer 6). the clock lines then connect to the adc through vias placed in close proximity to the device. the clock lines are isolated from the supply lines, by virtue of the ground plane on layer 5. the digital output traces should be kept as short as possible to minimize capacitive loading. the ground plane on layer 2 beneath these traces should not be removed so that the digital ground return currents have an uninterrupted path back to the bypass capacitors. from cm to inn to inp oa1 oa2 oa3 r c2 r c1 r g1 r g2 positive input negative input r f1 r f1 figure 8. dc-coupled analog input configuration
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications ______________________________________________________________________________________ 15 grounding the practice of providing a split ground plane in an attempt to confine digital ground return currents has often been recommended in adc application literature. however, for converters such as the MAX1427, it is strongly recommended to employ a single, uninterrupt- ed ground plane. the MAX1427 ev kit achieves excel- lent dynamic performance with such a ground plane. the ep of the MAX1427 should be soldered directly to a ground pad on layer 1 with vias to the ground plane on layer 2. this provides excellent electrical and ther- mal connections to the printed circuit supply bypassing the MAX1427 ev kit uses 220f capacitors on each supply line (av cc , dv cc , and drv cc ) to provide low- frequency bypassing. the loss (series resistance) associated with these capacitors is actually of some benefit in eliminating high-q supply resonances. ferrite beads are also used on each of the supply lines to enhance supply bypassing (figure 9). small value (0.01f to 0.1f) surface-mount capacitors should be placed at each supply pin or each grouping of supply pins to attenuate high-frequency supply noise (figure 9). it is recommended to place these capacitors on the topside of the board and as close to the device as possible with short connections to the ground plane. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. however, the static linearity parameters for the MAX1427 are mea- sured using the histogram method with an input fre- quency of 15mhz. MAX1427 15 d0 d14 av cc dv cc bypassing adc level bypassing board level 0.1 f drv cc gnd 0.1 f gnd 0.1 f gnd 10 f47 f 220 f av cc ferrite bead 10 f47 f 220 f dv cc ferrite bead 10 f47 f 220 f drv cc ferrite bead analog power-supply source digital power-supply source output driver power-supply source figure 9. grounding, bypassing, and decoupling recommendations for MAX1427
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications 16 ______________________________________________________________________________________ differential nonlinearly (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. the MAX1427 s dnl specification is measured with the his- togram method based on a 15mhz input tone. dynamic parameter definitions aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 4). aperture jitter the aperture jitter (t aj ) is the sample-to-sample varia- tion in the aperture delay. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc s reso- lution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the snr calcula- tion and should be considered when determining the snr in adc. for a near-full-scale analog input signal (-0.5dbfs to -1dbfs), thermal and quantization noise are uniformly distributed across the frequency bins. error energy caused by transfer function nonlinearities on the other hand is not distributed uniformly, but con- fined to the first few hundred odd-order harmonics. bts applications, which are the main target application for the MAX1427 usually do not care about excess noise and error energy in close proximity to the carrier frequency or to dc. these low-frequency and sideband errors are test frequency artifacts and are of no conse- quence to the bts channel sensitivity. they are there- fore excluded from the snr calculation. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components excluding the fundamen- tal and the dc offset. single-tone spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal component) to the rms value of the next-largest noise or harmonic distortion compo- nent. sfdr is usually measured in dbc with respect to the carrier frequency amplitude or in dbfs with respect to the adc s full-scale range. two-tone spurious-free dynamic range (sfdr tt ) sfdr tt represents the ratio of the rms value of either input tone to the rms value of the peak spurious com- ponent in the power spectrum. this peak spur can be an intermodulation product of the two input test tones. two-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -7db full scale. gnd 1 gnd 2 gnd 3 clkp 4 clkn 5 gnd 6 av cc 7 av cc 8 gnd 9 inp 10 inn 11 gnd 12 cm 13 gnd 14 drv cc 42 drv cc 41 d7 40 d6 39 d5 38 d4 37 d3 36 d2 35 d1 34 d0 33 dor 32 drv cc 31 gnd 30 dv cc 29 gnd 15 gnd 16 gnd 17 18 19 gnd 20 av cc 21 av cc av cc av cc av cc av cc av cc 22 gnd 23 24 25 gnd gnd 26 27 28 gnd 56 gnd 55 ep gnd 54 53 52 drv cc 51 gnd 50 gnd dav d14 d12 d11 d8 49 d13 48 47 46 d9 d10 45 44 43 MAX1427 top view qfn pin configuration
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications ______________________________________________________________________________________ 17 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 56l thin qfn.eps
MAX1427 15-bit, 80msps adc with -79.3dbfs noise floor for baseband applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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